FIG. 1 shows an example of a CMOS integrated circuit chip that includes an array of active pixel sensors 30 and a controller 32 that provides timing and control signals to enable reading out signals that are stored in the pixels. Arrays have dimensions of n by m pixels and, in general, the size of array 30 will depend on the particular implementation. The imager is read out a row at a time using a column parallel readout architecture. The controller 32 selects a particular row of pixels in array 30 by controlling the operation of vertical addressing circuit 34 and row drivers 40. Charge signals stored in the selected row of pixels are provided to a readout circuit 42. The pixels of the columns can be read out sequentially using a horizontal addressing circuit 44. Typically, each pixel provides a reset output signal, Vout1, and a signal representing accumulated charge during an integration period, Vout2, which are provided at the output of readout circuit 42.
As shown in FIG. 2, array 30 includes multiple columns 49 of CMOS active pixel sensors 50. Each column 49 includes multiple rows of sensors 50. Signals from the active pixel sensors 50 in a particular column can be read out to a readout circuit 52 associated with that column. Signals stored in the readout circuits 52 can be sent to an output stage 54, which is common to the entire array of pixels 30. The analog output signals can then be sent, for example, to an analog-to-digital converter (ADC).
It will be appreciated that the ADC is assumed to be external to the column readout circuits 52. It is also possible for the ADC to be located within the column readout circuits. In the latter case, output signals 70 and 72, in FIG. 2, would be the A/D converted outputs.
Although typically used in CCD sensors, binning techniques are being developed for CMOS active pixel sensors. Summing small neighborhoods of pixels together on a chip into larger “super-pixels” is known as binning and allows the user to trade off imager resolution for other operational parameters. Binning is usually done in square neighborhoods, such as 2×2, which decreases resolution by 2× in both the x and y directions. In some cases, binning may also be done in rectangular neighborhoods, such as 3×5, which sums 15 pixels together resulting in decreased resolution by 3 in the x direction and by 5 in the y direction.
One reason for implementing binning is to capture higher quality images at low-light levels. Since the camera can electronically be switched from full resolution to binning modes, the same camera can be used to provide high resolution images when light levels are adequate, and lower resolution images when light is scarce.
Binning can also be useful for a variety of other reasons. For example, since on-chip binning reduces the number of pixels which must be processed by the sensor's output amplifier, the frame rate of the camera can be increased when operating in a binning mode. This allows the camera to trade-off frame rate for resolution.
Binning is also used occasionally to provide physically large pixels when needed in some optical configurations. In some applications (particularly low light), a camera user may not need extremely high resolution, but may wish to have a pixel size of, for example, 56 microns on each side. Finding a commercially available chip with a 56-micron pixel would be difficult and would require a custom sensor development at a large expense. A simple alternative would be to use a 2K×2K chip with 14-micron pixels. By placing this chip in a 4×4 binning mode, the camera user can obtain an equivalent pixel size of 14×4=56 microns at a resolution of 512×512 using an off-the-shelf chip.
Manufacturing yield in the image sensor market is very important. After chip fabrication of an image sensor, the chip is tested to find failed components. A failure is typically corrected by skipping the failed component, using a redundant component.
A cell failure of an image sensor can be corrected easily by redundant cells. However, the image sensor has difficulty in correcting a column failure, due to the fixed array structure of an imager. Column failures can be corrected by skipping the failed column using a redundant column. This correction is not a good solution, however, because by simply skipping the failed column, features like binning (or summing) become unavailable to the camera user.
The present invention, as will be described, provides built-in correction circuits for column failures, without destroying binning (or summing) modes of operation.